AMD Kaveri APU Architecture Overview


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AMD Kaveri APU Architecture Overview

By Hank Tolman

Today marks the release of the latest in a long line of AMD Accelerated Processing Units. Benchmark Reviews has been there for each one of the previous APU releases, and we would be remiss if we didn’t provide you with the latest news regarding this release. It has been a long road since Llano, the very first generation of AMD APUs, was announced just three short years ago at CES 2011. That processor brought together AMD’s long held vision of putting a discrete level GPU on the same die as the CPU; a vision that started back with the Fusion project and AMD’s acquisition of ATI.


Llano put K10 CPU cores and a Radeon HD 6000 series GPU on the same die and introduced us to the FM1 socket. The Fusion project was then reformed as the Heterogeneous Systems Architecture (HSA). After Llano came Trinity, the second generation of APUs featuring Piledriver CPU cores and a Radeon HD 7000 series GPU. Trinity also introduced the FM2 socket. The third generation of AMD APUs, codenamed Richland, was more of a revamping of Trinity, and stuck with Piledriver CPU cores (turbocharged) and upgraded the GPU to a Radeon HD 8000 series.

That brings us up to speed and leads us into the huge press conference held just prior to CES 2014 by AMD to announce and explain the fourth generation of AMD APUs, codenamed Kaveri. During the AMD Tech Day presentations held in early January 2014, I must have heard the word “excited” about ten thousand times from AMD presenters showcasing the new performance and advancements of the Kaveri APU. Kaveri, it seems, is the embodiment of HSA that AMD has been working towards since Llano. Built on AMD’s new Steamroller CPU cores and combined with an R7 series GPU, the Kaveri APU brings the two together like no processor before it. The key to “excitement” surrounding the Kaveri launch actually lies in the way CPU and the GPU can work together to provide the best APU performance we have seen from AMD.


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